The design of predictable multi-core processors which support time-triggered software architectures
thesisposted on 03.11.2014, 10:09 by Keith Florence Athaide
Safety-critical systems – such as those used in the medical, automotive and aerospace fields – have a crucial dependence on the reliable functioning of one or more embedded processors. In such systems, a co-operative software design methodology can be used to guarantee a high degree of reliability; when coupled with a time-triggered architecture, this methodology can result in robust and predictable systems with a comparatively simple software design, low operating system overhead, easier testability, greater certification support and tight jitter control. Nevertheless, the use of a co-operative design methodology is not always appropriate, since it may negatively affect system responsiveness and can add to the maintenance costs. Many alternatives have been researched and implemented over the past few decades to address such concerns, albeit by compromising on some of the benefits this architecture provides. This thesis makes five main contributions to tackle the major obstacles to single-processor time-triggered co-operative designs: • it proposes and describes the implementation of a novel multi-core processor with two capable software scheduler implementations that allow application software to be designed as for a single-core system; • it describes the internalisation of these scheduler implementations into hardware which allows application software to use all available computing capacity; • it describes a hardware technique to eliminate the variations in starting times of application software, thereby increasing the stability of applications; • it describes the implementation of a hardware technique for sharing input/output resources amongst application software with increased determinism by leveraging the time-triggered nature of the underlying system; • it describes the implementation of a predictable processor that supports purely co-operative software and is suitable for the secondary cores on a multi-core design (due to its small size). Overall, the contributions of this thesis both increase system responsiveness and lessen the impact of seemingly innocuous maintenance activities.